1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device with a memory cell section including floating-gate type transistors and a capacitor section including capacitors, and a method of fabricating the device.
2. Description of the Related Art
Generally, it is important for semiconductor memory devices to increase the capacitance of capacitors and to decrease the chip area.
FIG. 1 shows schematically the layout of a prior-art semiconductor memory device, which has the memory cell section S101 and the capacitor section S102 on a semiconductor substrate.
The prior-art semiconductor memory device of FIG. 1 is fabricated in the following way.
First, as shown in FIG. 2A, a silicon dioxide (SiO2) layer (not shown) with a thickness of 3 nm to 20 nm is formed on the surface of a p-type semiconductor substrate (e.g., a single-crystal silicon substrate) 110. A silicon nitride (SiNx) layer (not shown) with a thickness of 100 nm to 200 nm is formed on the SiO2 layer and is patterned to have a specific plan shape. Then, a SiO2 layer is selectively formed on the exposed surface of the substrate 110 from the patterned SiNx layer, forming an isolation dielectric 114. The isolation dielectric 114 thus formed defines active regions 110a on the substrate 110.
Then, a first gate dielectric layer 112 with a thickness of 5 nm to 15 nm is selectively formed on the exposed surface of the substrate 110 in the active regions 110a by a thermal oxidation process.
An n-type polysilicon layer with a thickness of approximately 50 nm to 200 nm, which is doped with an appropriate dopant such as phosphorus (P), is formed over the entire substrate 110 to cover the isolation dielectric 114 and the active regions 110a. After a patterned resist film 118 is formed on the polysilicon layer, the polysilicon layer is selectively etched to form floating gates 120 on the gate dielectric layer 112 in the memory cell section S101 and lower electrodes 122 on the isolation dielectric 114 in the capacitor section S102 using the film 118 as a mask. The state at this stage is shown in FIG. 2A.
After the patterned resist film 118 is removed, a dielectric layer 124 with a thickness of approximately 10 nm to 20 nm is formed over the substrate 110 by a thermal oxidation or chemical vapor deposition (CVD) process, covering the floating gates 120 in the memory cell section S101 and the lower electrodes 122 in the capacitor section S102. The layer 124 has a three-layer structure; i.e., the layer 124 is formed by a SiO2 sublayer, a SiNx sublayer, and a SiO2 sublayer stacked in this order. Thus, the layer 124 is a so-called xe2x80x9cONOxe2x80x9d layer. Next, an n-type polysilicon layer 126 with a thickness of approximately 100 nm to 200 nm is formed on the dielectric (ONO) layer 124 over the entire substrate 110.
After a patterned resist film 128 is formed on the polysilicon layer 126, the polysilicon layer 126 and the dielectric (ONO) layer 124 are selectively etched to define the memory cell section S101 and the capacitor section S102 on the substrate 110 using the film 128 as a mask. The state at this stage is shown in FIG. 2B.
As seen from FIG. 2B, the remaining dielectric layer 124 in the memory cell section S101 forms a second gate dielectric layer 124a and at the same time, the remaining polysilicon layer 126 in the memory cell section S101 forms control gates 130. The remaining dielectric layer 124 in the capacitor section S102 forms a capacitor dielectric layer 124b. 
Subsequently, after the resist film 128 is removed, a patterned resist film 132 is formed on the polysilicon layer 126 thus patterned. Then, the polysilicon layer 126 is selectively etched to define the capacitors in the capacitor section S102 using the film 132 as a mask. The state at this stage is shown in FIG. 2C. As seen from FIG. 2C, the remaining polysilicon layer 126 in the capacitor section S102 is divided to form upper electrodes 134.
Thereafter, the patterned resist film 132 is removed, resulting in the structure shown in FIG. 2D. Specifically, in the memory cell section S101, the first gate dielectric layer 112, the floating gate 120, the second gate dielectric layer 124a, and the control gate 130 in each of the active regions 110a constitute a floating-gate type transistor. In the capacitor section S102, the lower electrode 122, the common capacitor dielectric 124b, and the upper electrode 134 constitute a capacitor.
As explained above, with the prior-art semiconductor memory device, each of the capacitors is located on the isolation dielectric 114 and is formed by the lower electrode 122, the common capacitor dielectric 124b, and the upper electrode 134. It is unlike the former, typical capacitor structure that is formed by a diffusion region in the substrate 110, a gate dielectric layer, and a gate electrode. This is to suppress the parasitic capacitance existing in the capacitor section S102.
In recent years, the capacitor structure of the prior-art semiconductor memory device of FIG. 1 tends to be insufficient to meet the need of further decreasing the chip area. To meet this need, an improvement has been created and disclosed, in which recesses are uniformly formed on the surfaces of the lower electrodes 122 in the capacitor section S102. This is to expand the surface area of each lower electrode 122, thereby increasing the capacitance. Therefore, in this improvement, the chip area can be reduced without decreasing the capacitance of each capacitor.
However, in the improvement, there arises a problem about the withstand voltage. Specifically, since the lower electrode 122 has the recesses on its surface, the capacitor dielectric 124b extends along the recesses, resulting in a problem of degradation of the withstand voltage of the dielectric 124b. To ensure satisfactory withstand voltage, the dielectric 124b needs to be thicker, which means that the second gate dielectric layer 124a of each transistor in the memory cell area S101 needs to be thicker as well. This is because the capacitor dielectric layer 124b and the second gate dielectric layer 124a are formed by the same dielectric layer 124. As a result, there arises a problem that the performance or characteristic of the transistors in the memory cell section S101 deteriorates.
As explained above, when the above-described improvement is adopted to increase the capacitance, the withstand voltage of the capacitor dielectric 124b in the capacitor section S102 degrades. When the capacitor dielectric 124b is formed thicker to ensure its sufficient withstand voltage, the performance or characteristic of the transistors in the memory cell section S101 deteriorates.
Accordingly, an object of the present invention is to provide a semiconductor memory device that makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric, and a method of fabricating the device.
Another object of the present invention is to provide a semiconductor memory device that makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the performance or characteristic of the memory cell section, and a method of fabricating the device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor memory device is provided. This device comprises:
(a) a semiconductor substrate with an isolation dielectric;
the isolation dielectric defining active regions on the substrate;
(b) a memory cell section formed on the substrate;
the memory cell section including floating-gate type transistors formed in the active regions;
each of the transistors having a first gate dielectric, a floating gate formed on the first gate dielectric, a second gate dielectric formed on the floating gate, and a control gate formed on the second gate dielectric; and
(c) a capacitor section formed on the substrate;
the capacitor section including capacitors formed on the isolation dielectric of the substrate;
each of the capacitors having a lower electrode formed on the isolation dielectric, a capacitor dielectric formed on the lower electrode, and an upper electrode formed on the capacitor dielectric;
a first part of the capacitors being designed to be applied with a first voltage and a second part of the capacitors being applied with a second voltage on operation, where the first voltage is lower than the second voltage;
each of the first part of the capacitors having a recess formed on the lower electrode, thereby increasing its capacitance.
With the semiconductor memory device according to the first aspect of the present invention, each of the first part of the capacitors has the recess formed on the lower electrode, thereby increasing its capacitance. Due to the formation of the recess, the withstand voltage of the capacitor dielectric of the first part of the capacitors degrades. However, the first part of the capacitors is/are designed to be applied with the first voltage lower than the second voltage. As a result, the formation of the recess will not cause any disadvantage relating to the withstand voltage.
On the other hand, each of the second part of the capacitors, which are designed to be applied with the second voltage higher than the first voltage, has no recess. Therefore, the withstand voltage of the capacitor dielectric is prevented from degrading.
Accordingly, the capacitance of the capacitors can be increased without degrading the withstand voltage and without increasing the chip area.
In a preferred embodiment of the semiconductor memory device according to the first aspect, the recess of the lower electrode of each of the first part of the capacitors is less than a thickness of the lower electrode. In this embodiment, there is an additional advantage that the obtainable capacitance is further increased because the part of the lower electrode at the bottom of the recess contributes the capacitance generation of each of the first part of the capacitors.
In another preferred embodiment of the semiconductor memory device according to the first aspect, the upper electrode of each of the first or second part of the capacitors is narrower than the lower electrode thereof. In this embodiment, there is an additional advantage that the capacitor dielectric (and the second gate dielectric of each of the transistors in the memory cell section) can be formed thinner. This is because the part of the capacitor dielectric on the side face of the lower electrode, which tends to be thinner than that on the upper surface thereof, is not used and therefore, the withstand voltage of the capacitor does not degrade.
In still another preferred embodiment of the semiconductor memory device according to the first aspect, the upper electrode of each of the second part of the capacitors is narrower than the lower electrode thereof while the upper electrode of each of the first part of the capacitors is not narrower than the lower electrode thereof. In this embodiment, there is an additional advantage that the capacitor dielectric (and the second gate dielectric of each of the transistors in the memory cell section) can be formed thinner while the capacitance is increased.
According to a second aspect of the present invention, a method of fabricating a semiconductor memory device is provided, where the device includes a memory cell section including floating-gate type transistors and a capacitor section including capacitors. This method comprises the steps of:
(a) forming an isolation dielectric on a semiconductor substrate;
the isolation dielectric defining active regions on the substrate;
(b) selectively forming a first dielectric layer on the active regions of the substrate;
(c) forming a first conductive layer on the first dielectric layer and the isolation dielectric;
(d) patterning the first conductive layer to form floating gates of the floating-gate type transistors on the first dielectric layer in the memory cell section and lower electrodes of the capacitors on the isolation dielectric in the capacitor section;
a first part of the capacitors being designed to be applied with a first voltage and a second part of the capacitors being applied with a second voltage on operation, where the first voltage is lower than the second voltage;
(e) forming a recess on each of the lower electrodes of the first part of the capacitors;
(f) forming a second dielectric layer to cover the floating gates of the transistors and the lower electrodes of the capacitors;
(g) forming a second conductive layer on the second dielectric layer; and
(h) pattering the second conductive layer and the second dielectric layer to form control gates of the transistors and upper electrodes of the capacitors;
wherein each of the transistors is constituted by the first gate dielectric, the floating gate formed on the first gate dielectric, the second gate dielectric formed on the floating gate, and the control gate formed on the second gate dielectric;
and wherein each of the capacitors is constituted by the lower electrode, the capacitor dielectric formed on the lower electrode, and the upper electrode formed on the capacitor dielectric.
With the method according to the second aspect of the present invention, the semiconductor memory device having a memory cell section including floating-gate type transistors and the capacitor section including capacitors according to the first aspect is fabricated.
In a preferred embodiment of the method according to the second aspect, the recess of the lower electrode of each of the first part of the capacitors is set to be less than a thickness of the lower electrode in the step (e). In this embodiment, there is an additional advantage that the obtainable capacitance is further increased because the part of the lower electrode at the bottom of the recess contributes the capacitance generation of each of the first part of the capacitors.
In another preferred embodiment of the method according to the second aspect, the upper electrode of each of the first or second part of the capacitors is set to be narrower than the lower electrode thereof. In this embodiment, there is an additional advantage that the capacitor dielectric (and the second gate dielectric of each of the transistors in the memory cell section) can be formed thinner. This is because the part of the capacitor dielectric on the side face of the lower electrode, which tends to be thinner than that on the upper surface thereof, is not used and therefore, the withstand voltage of the capacitor does not degrade.
In still another preferred embodiment of the method according to the second aspect, the upper electrode of each of the second part of the capacitors is set to be narrower than the lower electrode thereof while the upper electrode of each of the first part of the capacitors is not set to be narrower than the lower electrode thereof. In this embodiment, there is an additional advantage that the capacitor dielectric (and the second gate dielectric of each of the transistors in the memory cell section) can be formed thinner. This is because the part of the capacitor dielectric on the side face of the lower electrode, which tends to be thinner than that on the upper surface thereof, is not used in the second part of the capacitors to which the second voltage higher than the first voltage is applied.